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description the hctl-1100 series is a high performance, general purpose motion control ic, fabricated in avago cmos technology. it frees the host processor for other tasks by performing all the time-intensive functions of digital motion control. the programmability of all control parameters provides maximum flexibility and quick design of control systems with a minimum number of components. in addition to the hctl-1100, the complete control system consists of a host processor to specify commands, an amplifier, and a motor with an incremental encoder (such as the hp heds-5xxx, -6xxx, -9xxx series). no analog compensation or velocity feedback is necessary. pinouts esd warning: normal handling precautions should be taken to avoid static discharge. features low power cmos pdip and plcc versions available enhanced version of the hctl-1000 dc, dc brushless, and step motor control position and velocity control programmable digital filter and commutator 8-bit parallel, and pwm motor command ports ttl compatible sync pin for coordinating multiple hctl-1100 ics 100 khz to 2 mhz operation encoder input port hctl-1100 series general purpose motion control ics data sheet
2 applications typical applications for the hctl-1100 include printers, medical instruments, material handling machines, and industrial automation. note: avago technologies encoders are not recommended for use in safety critical applications. eg. abs braking systems, power steering, life comparison of hctl-1100 and hctl-1000 description hctl-1100 hctl-1000 max. supply current 30 ma 180 ma max. power dissipation 165 mw 950 mw max. tri-state output leakage current 150 na 10 a operating frequency 100 khz-2 mhz 1 mhz-2 mhz operating temperature range -20 c to +85 c0 c to 70 c storage temperature range -55 c to +125 c-40 c to +125 c synchronize 2 or more ics yes preset actual position registers yes read flag register yes limit and stop pins must be pulled can be left up to v dd if floating if not not used. used. hard reset required recommended plcc package available yes system block diagram support systems and critical care medical equipment. please contact sales representative if more clarification is needed. hctl-1100 vs. hctl-1000 the hctl-1100 is designed to replace the hctl-1000. some differences exist, and some enhancements have been added.
3 theory of operation the hctl-1100 is a general pur- pose motor controller which provides position and velocity control for dc, dc brushless and stepper motors. the internal block diagram of the hctl-1100 is shown in figure 1. the hctl- 1100 receives its input commands from a host processor and position feedback from an incremental encoder with quadra- ture output. an 8-bit bi-directional multiplexed address/data bus interfaces the hctl-1100 to the host processor. the encoder the resident position profile generator calculates the neces- sary profiles for trapezoidal pro- file control and integral velocity control. the hctl-1100 com- pares the desired position (or velocity) to the actual position (or velocity) to compute compensated motor commands using a pro- grammable digital filter d(z). the motor command is externally available at the motor command port as an 8-bit byte and at the pwm port as a pulse width modulated (pwm) signal. the hctl-1100 has the capability of providing electronic commu- tation for dc brushless and stepper motors. using the encoder position information, the motor phases are enabled in the correct sequence. the commu- tator is fully programmable to encompass most motor/encoder combinations. in addition, phase overlap and phase advance can be programmed to improve torque ripple and high speed perform- ance. the hctl-1100 contains a number of flags including two externally available flags, profile and initialization, which allow the user to see or check the status of the controller. it also has two emergency inputs, limit and stop, which allow operation of the hctl-1100 to be interrupted under emergency conditions. the hctl-1100 controller is a digitally sampled data system. while information from the host processor is accepted asyn- chronously with respect to the control functions, the motor command is computed on a discrete sample time basis. the sample timer is programmable. package dimensions feedback is decoded into quadrature counts and a 24-bit counter keeps track of position. the hctl-1100 executes any one of four control algorithms selected by the user. the four control modes are: ?position control ?proportional velocity control ?trapezoidal profile control for point to point moves ?integral velocity control with continuous velocity profiling using linear acceleration 4.83 0.190 1.27 0.050 0.15 0.006 0-15 13.72 0.540 13.72 0.540 0.25 0.010
4 figure 1. internal block diagram. figure 2. operating mode flowchart.
5 electrical specifications absolute maximum ratings operating temperature, t a ................................................................... -20 c to 85 c storage temperature, t s ...................................................................... -55 c to 125 c supply voltage, v dd ...................................................................................... - 0.3 v to 7 v input voltage, v in ......................................................................... - 0.3 v to v dd +0.3 v maximum operating clock frequency, f clk ............................................... 2 mhz dc electrical characteristics v dd = 5 v 5%; t a = -20 c to +85 c parameter symbol min. typ. max. units test conditions supply voltage v dd 4.75 5.00 5.25 v supply current i dd 15 30 ma input leakage current i in 10 100 na v in = 0.00 and 5.25 v input pull-up current sync pin i pu - 40 150 av in = 0.00 v tristate output leakage i oz 10 -150 na sync, limit, stop current pin #35 (pdip) v out = -0.3 to 5.25 v pin #38 (plcc) input low voltage v il -0.3 0.8 v input high voltage v ih 2.0 v dd v output low voltage v ol -0.3 0.4 v i ol = 2.2 ma output high voltage v oh 2.4 v dd vi oh = -200 a power dissipation p d 75 165 mw input capacitance c in 20 pf output capacitance c out 100 pf
6 ac electrical characteristics v dd = 5 v 5%; t a = -20 c to +85 c; units = nsec clock frequency formula* 2 mhz 1 mhz id # signal symbol min. max. min. max. min. max. 1 clock period (clk) t cper 500 1000 2 pulse width, clock high t cpwh 230 300 3 pulse width, clock low t cpwl 200 200 200 4 clock rise and fall time t cr 50 50 50 5 input pulse width reset t irst 2500 5000 5 clk 6 input pulse width stop, limit t ip 600 1100 1 clk + 100 ns 7 input pulse width index, index t ix 1600 3100 3 clk + 100 ns 8 input pulse width cha, chb t iab 1600 3100 3 clk + 100 ns 9 delay cha to chb transition t ab 600 1100 1 clk + 100 ns 10 input rise/fall time cha, chb, index t iabr 450 900 900 (clk < 1 mhz) 11 input rise/fall time reset, ale, cs, oe, stop, limit t ir 50 50 50 12 input pulse width ale, cs t ipw 80 80 80 13 delay time, ale fall to cs fall t ac 50 50 50 14 delay time, ale rise to cs rise t ca 50 50 50 15 address setup time before ale fall t asr1 20 20 20 16 address setup time before cs t asr 20 20 20 fall 17 write data setup time before cs rise t dsr 20 20 20 18 address/data hold time t h 20 20 20 19 setup time, r/w before cs rise t wcs 20 20 20 20 hold time, r/w after cs rise t wh 20 20 20 21 delay time, write cycle, cs rise to ale fall t csal 1700 3400 3.4 clk 22 delay time, read/write, cs rise to cs fall t cscs 1500 3000 3 clk 23 write cycle, ale fall to ale fall for next write t wc 1830 3530 3.7 clk
7 clock frequency formula* 2 mhz 1 mhz id # signal symbol min. max. min. max. min. max. 24 delay time, cs rise to oe fall t csoe 1700 3200 3 clk + 200 ns 25 delay time, oe fall to data bus valid t oedb 100 100 100 26 delay time, cs rise to data bus valid t csdb 1800 3300 3 clk + 300 ns 27 input pulse width oe t ipwoe 100 100 100 28 hold time, data held after oe rise t doeh 20 20 20 29 delay time, read cycle, cs rise to ale fall t csalr 1820 3320 3 clk + 320 ns 30 read cycle, ale fall to ale fall for next read t rc 1950 3450 3 clk + 450 ns 31 output pulse width, prof, init, pulse, sign, pha-phd, mc port t of 500 1000 1 clk 32 output rise/fall time, prof, init, pulse, sign, pha-phd, mc port t or 20 150 20 150 20 150 33 delay time, clock rise to output rise t ep 20 300 20 300 20 300 34 delay time, cs rising to mc port valid t csmc 1600 3200 3.2 clk 35 hold time, ale high after cs rise t alh 100 100 100 36 pulse width, ale high t alpwh 100 100 100 37 pulse width, sync low t sync 9000 18000 18 clk *general formula for determining ac characteristics for other clock frequencies (clk), between 100 khz and 2 mhz. ac electrical characteristics (continued).
8 hctl-1100 i/o timing diagrams input logic level values are the ttl logic levels v il = 0.8 v and v ih = 2.0 v. output logic levels are v ol = 0.4 v and v oh = 2.4 v.
9 hctl-1100 i/o timing diagrams there are three different timing configurations which can be used to give the user flexibility to interface the hctl-1100 to most microprocessors. see the i/o interface section for more details.
10 hctl-1100 i/o timing diagrams
11 hctl-1100 i/o timing diagrams
12 pin descriptions and functions input/output pins pin number symbol pdip plcc description ad0/db0- 2-7 3-8 address/data bus ?lower 6 bits of 8-bit i/o port which are ad5/db5 multiplexed between address and data. db6, db7 8, 9 9, 10 data bus ?upper 2 bits of 8-bit i/o port used for data only. input signals pin number symbol pdip plcc description cha/chb 31, 30 34, 33 channel a, b ?input pins for position feedback from an incremental shaft encoder. two channels, a and b, 90 degrees out of phase are required. index 33 36 index pulse ?input from the reference or index pulse of an incre- mental encoder. used only in conjunction with the commutator. either a low or high true signal can be used with the index pin. see timing diagrams and encoder interface section for more detail. r/w 37 41 read/write ?determines direction of data exchange for the i/o port. ale 38 42 address latch enable ?enables lower 6 bits of external data bus into internal address latch. cs 39 43 chip select ?performs i/o operation dependent on status of r/w line. for a write, the external bus data is written into the internal addressed location. for read, data is read from an internal location into an internal output latch. oe 40 44 output enable ?enables the data in the internal output latch onto the external data bus to complete a read operation. limit 14 15 limit switch ?an internal flag which when externally set, triggers an unconditional branch to the initialization/idle mode before the next control sample is executed. motor command is set to zero. status of the limit flag is monitored in the status register. stop 15 16 stop flag ?an internal flag that is externally set. when flag is set during integral velocity control mode, the motor command is decelerated to a stop. reset 36 40 reset ?a hard reset of internal circuitry and a branch to reset mode. extclk 34 37 external clock v dd 11, 35 12, 38 voltage supply ?both v dd pins must be connected to a 5.0 volt supply. gnd 10, 32 1, 11, circuit ground 23, 35 sync 1 2 used to synchronize multiple hctl-1100 sample timers. nc 17, 39 not connected. these pins should be left floating.
13 output pins pin number symbol pdip plcc description mc0-mc7 18-25 20-22, motor command port ?8-bit output port which contains the digital 24-28 motor command adjusted for easy bipolar dac interfacing. mc7 is the most significant bit (msb). pulse 16 18 pulse ?pulse width modulated signal whose duty cycle is proportional to the motor command magnitude. the frequency of the signal is external clock/100 and pulse width is resolved into 100 external clocks. sign 17 19 sign ?gives the sign/direction of the pulse signal. pha-phd 26-29 29-32 phase a, b, c, d ? phase enable outputs of the commutator. prof 12 13 profile flag ?status flag which indicates that the controller is execut- ing a profiled position move in the trapezoidal profile control mode. init 13 14 initialization/idle flag ?status flag which indicates that the controller is in the initialization/idle mode. pin functionality sync pin the sync pin is used to syn- chronize two or more ics. it is only valid in the init/idle mode (see operating the hctl-1100). when this pin is pulled low, the internal sample timer is cleared and held to zero. when the level on the pin is returned to high, the internal sample timer instantly starts counting down from the programmed value. connecting all sync pins together in the system and pulsing the sync signal from the host processor will synchronize all controllers. limit pin this emergency-flag input is used to disable the control modes of the hctl-1100. a low level on this input pin causes the internal limit flag to be set. if this pin is not used, it must be pulled up to v dd . if it is not connected, the pin could float low, and possibly trigger a false emergency condition. the limit flag, when set in any control mode, causes the hctl- 1100 to go into the initialization/ idle mode, clearing the motor command and causing an imme- diate motor shutdown. when the limit flag is set, none of the three control mode flags (f0, f3, or f5) are cleared as the hctl-1100 enters the initialization/idle mode. the user should be aware that these flags are still set before commanding the hctl-1100 to re-enter one of the four control modes from initialization/idle mode. in general, the user should clear all control mode flags after the limit pin has been pulled low, then proceed. stop pin the stop flag affects the hctl- 1100 only in the integral velocity mode. when a low level is present on this emergency-flag input, the internal stop flag is set. if this pin is not used, it must be pulled up to v dd . if it is not connected, the pin could float low, and possibly trigger a false emergency condition. when the stop flag is set, the system will come to a decelerated stop and stay in this mode with a command velocity of zero until the stop flag is cleared and a new command velocity is specified. notes on limit and stop flags stop and limit flags are set by a low level input at their respective pins. the flags can only be cleared when the input to the corresponding pin goes high, signifying that the emergency condition has been corrected, and a write to the status register (r07h) is executed. that is, after the emergency pin has been set and cleared, the flag also must be cleared by writing to r07h. any word that is written to r07h after the emergency pin is set and cleared will clear the emergency flag. the lower four bits of that word will also reconfigure the status register.
14 encoder input pins (cha, chb, index) the hctl-1100 accepts ttl compatible outputs from 2 and 3 channel incremental encoders such as the heds-5xxx, 6xxx, and 9xxx series encoders. channels a and b are internally decoded into quadrature counts which increment or decrement the 24-bit position counter. for example, a 500-count encoder is decoded into 2000 quadrature counts per revolution. the position counter will be incre- mented when channel b leads channel a. the index channel is used only for the commutator and its function is to serve as a reference point for the internal ring counter. the hctl-1100 employs an internal 3-bit state delay filter to remove any noise spikes from the encoder inputs to the hctl-1100. this 3-bit state delay filter requires the encoder inputs to remain stable for three consec- utive clock rising edges for an encoder pulse to be considered valid by the hctl-1100? actual position counter (i.e., an encoder pulse must remain at a logic level high or low for three consecutive clock rising edges for the hctl- 1100? actual position counter to be incremented or decremented.) the designer should therefore generally avoid creating the encoder pulses of less than 3 clock cycles. the index signal of an encoder is used in conjunction with the commutator. it resets the internal ring counter which keeps track of the rotor position so that no cumulative errors are generated. the index pin of the hctl-1100 also has a 3-bit filter on its input. the index pin is active low and level transition sensitive . it detects a valid high-to-low transition and qualifies the low input level through the 3-bit filter. at this point, the index signal is internally detected by the commutator logic. this type of configuraiton allows an index or index signal to be used to gen- erate the reference mark for commutator operation as long as the ac specifications for the index signal are met. motor command port (mc0-mc7) the 8-bit motor command port consists of register r08h whose data goes directly to external pins mc0-mc7. mc7 is the most significant bit. r08h can be read and written to, however, it should be written to only during the initialization/idle mode. during any of the four control modes, the controller writes the motor command into r08h. this topic is further discussed in the ?egister section?under ?otor command register r08h? pulse width modulation (pwm) output port (pulse, sign) the pwm port consists of the pulse and sign pins. the pwm port outputs the motor command as a pulse width modulated signal with the correct polarity. this topic is further discussed in the ?egister section?under ?wm motor command register r09h? trapezoid profile pin (prof) the trapezoid profile pin is internally connected to software flag bit 4 in the status register. this flag is also represented by bit 0 in the flag register (r00h). see the ?egister section?for more information. both the pin and the flag indicate the status of a trapezoid profile move. when the hctl-1100 begins a trapezoid move, this flag is set by the controller (a high level appears on the pin), indicating the move is in progress. when the hctl-1100 finishes the move, this flag is cleared by the controller. note that the instant the flag is cleared may not be the same instant the motor stops. the flag indicates the completion of the command profile, not the actual profile. if the motor is stalled during the move, or cannot physically keep up with the move, the flag will be cleared before the move is finished. init/idle pin (init) this pin indicates that the hctl- 1100 is in the init/idle mode, waiting to begin control. this pin is internally connected to the software flag bit 5 in the status register r07h. this flag is also represented by bit 1 in the flag register (r00h) (see the ?egister section?for more information). commutator pins (pha-phd) these pins are connected only when using the commutator of the hctl-1100 to drive a brushless motor or step motor. the four pins can be programmed to energize each winding on a multiphase motor.
15 figure 3. register block diagram. operation of the hctl-1100 registers the hctl-1100 operation is controlled by a bank of 64 8-bit registers, 35 of which are user accessible. these registers contain command and configura- tion information necessary to properly run the controller chip. the 35 user-accessible registers are listed in tables 1 and 2. the register number is also the address. a functional block diagram of the hctl-1100 which shows the role of the user- accessible registers is also included in figure 3. the other 29 registers are used by the internal cpu as scratch registers and should not be accessed by the user.
16 table 1. register reference by mode register user hex dec. function data type [1] access general control r00h r00d flag register r/w r05h r05d program counter scalar r/w r07h r07d status register - r/w [2] r0fh r15d sample timer scalar r/w r12h r18d read actual position msb 2? complement r [4] r13h r19d read actual position 2? complement r [4] /w [5] r14h r20d read actual position lsb 2? complement r [4] r15h r21d preset actual position msb 2? complement w [8] r16h r22d preset actual position 2? complement w [8] r17h r23d preset actual position lsb 2? complement w [8] output registers r07h r07d sign reversal inhibit - r/w [2] r08h r08d 8 bit motor command 2? complement+80h r/w r09h r09d pwm motor command 2? complement r/w filter registers r20h r32d filter zero, a scalar r/w r21h r33d filter pole, b scalar r/w r22h r34d gain, k scalar r/w commutator registers r07h r07d status register - r/w [2] r18h r24d commutator ring scalar [6,7] r/w r19h r25d velocity timer scalar w r1ah r26d x scalar [6,7] r/w r1bh r27d y phase overlap scalar [6,7] r/w r1ch r28d offset 2? complement [7] r/w r1fh r31d max. phase advance scalar [6,7] r/w position control mode r00h r00d flag register - r/w r12h r18d read actual position msb 2? complement r [4] r13h r19d read actual position 2? complement r [4] /w [5] r14h r20d read actual position lsb 2? complement r [4] r0ch r12d command position msb 2? complement r/w [3] r0dh r13d command position 2? complement r/w [3] r0eh r14d command position lsb 2? complement r/w [3]
17 table 1. (continued). register user hex dec. function data type access trapezoid profile control mode r00h r00d flag register - r/w r07h r07d status register - r/w [2] r12h r18d read actual position msb 2? complement r [4] r13h r19d read actual position 2? complement r [4] /w [5] r14h r20d read actual position lsb 2? complement r [4] r29h r41d final position lsb 2? complement r/w r2ah r42d final position 2? complement r/w r2bh r43d final position msb 2? complement r/w r26h r38d acceleration lsb scalar r/w r27h r39d acceleration msb scalar [6] r/w r28h r40d maximum velocity scalar [6] r/w integral velocity mode r00h r00d flag register - r/w r12h r18d read actual position msb 2? complement r [4] r13h r19d read actual position 2? complement r [4] /w [5] r14h r20d read actual position lsb 2? complement r [4] r26h r38d acceleration lsb scalar r/w r27h r39d acceleration msb scalar [6] r/w r3ch r60d command velocity 2? complement r/w proportional velocity mode r00h r00d flag register - r/w r12h r18d read actual position msb 2? complement r [4] r13h r19d read actual position 2? complement r [4] /w [5] r14h r20d read actual position lsb 2? complement r [4] r23h r35d command velocity lsb 2? complement r/w r24h r36d command velocity msb 2? complement r/w r34h r52d actual velocity lsb 2? complement r r35h r53d actual velocity msb 2? complement r notes: 1. consult appropriate section for data format and use. 2. upper 4 bits are read only. 3. writing to r0eh (lsb) latches all 24 bits. 4. reading r14h (lsb) latches data in r12h and r13h. 5. writing to r13h clears actual position counter to zero. 6. the scalar data is limited to positive numbers (00h to 7fh). 7. the commutator registers (r18h, r1ch, r1fh) have further limits which are discussed in the commutator section of this data s heet. 8. writing to r17h (r23d) latches all 24 bits (only in init/idle mode).
18 table 2. register reference table by register number register user hex dec. function mode used data type access r00h r00d flag register all r/w r05h r05d program counter all scalar w r07h r07d status register all r/w [2] r08h r08d 8 bit motor command port all 2? complement + 80h r/w r09h r09d pwm motor command port all 2? complement r/w r0ch r12d command position (msb) all except proportional 2? complement r/w [3] velocity r0dh r13d command position all except proportional 2? complement r/w [3] velocity r0eh r14d command position (lsb) all except proportional 2? complement r/w [3] velocity r0fh r15d sample timer all scalar r/w r12h r18d read actual position (msb) all 2? complement r [4] r13h r19d read actual position all 2? complement r [4] /w [5] r14h r20d read actual position (lsb) all 2? complement r [4] r15h r21d preset actual position (msb) init/idle 2? complement w [8] r16h r22d preset actual position init/idle 2? complement w [8] r17h r23d preset actual position (lsb) init/idle 2? complement w [8] r18h r24d commutator ring all scalar [6,7] r/w r19h r25d commutator velocity timer all scalar w r1ah r26d x all scalar [6] r/w r1bh r27d y phase overlap all scalar [6] r/w r1ch r28d offset all 2? complement [7] r/w r1fh r31d maximum phase advance all scalar [6,7] r/w r20h r32d filter zero, a all except proportional scalar r/w velocity r21h r33d filter pole, b all except proportional scalar r/w velocity r22h r34d gain, k all scalar r/w r23h r35d command velocity (lsb) proportional velocity 2? complement r/w r24h r36d command velocity (msb) proportional velocity 2? complement r/w r26h r38d acceleration (lsb) integral velocity and scalar r/w trapezoidal profile r27h r39d acceleration (msb) integral velocity and scalar [6] r/w trapezoidal profile r28h r40d maximum velocity trapezoidal profile scalar [6] r/w r29h r41d final position (lsb) trapezoidal profile 2? complement r/w r2ah r42d final position trapezoidal profile 2? complement r/w r2bh r43d final position (msb) trapezoidal profile 2? complement r/w r34h r52d actual velocity (lsb) proportional velocity 2? complement r r35h r53d actual velocity (msb) proportional velocity 2? complement r r3ch r60d command velocity integral velocity 2? complement r/w notes: 1. consult appropriate section for data format and use. 2. upper 4 bits are read only. 3. writing to r0eh (lsb) latches all 24 bits. 4. reading r14h (lsb) latches data in r12h and r13h. 5. writing to r13h clears actual position counter to zero. 6. the scalar data is limited to positive numbers (00h to 7fh). 7. the commutator registers (r18h, r1ch, r1fh) have further limits which are discussed in the commutator section of this data s heet. 8. writing to r17h (r23d) latches all 24 bits (only in init/idle mode).
19 motor by using the commutator. (see ?ffset register?description in the ?ommutator section.? f5 ?ntegral velocity control ?set by the user to specify integral velocity control. also set and cleared by the hctl-1100 during execution of the trapezoidal profile mode. this is transparent to the user except when the limit flag is set (see ?mergency flags section). writing to the flag register when writing to the flag register, only the lower four bits are used. bit 3 indicates whether to set or clear a certain flag, and bits 0,1,and 2 indicate the desired flag. the following table shows the bit map of the flag register: bit number function 7-4 don? care 31 = set 0 = clear 2 ad2 1 ad1 0 ad0 the following table outlines the possible writes to the flag register: flag set clear f0 08h 00h f1 - - f2 0ah 02h f3 0bh 03h f4 0ch 04h f5 0dh 05h reading the flag register reading register r00h returns the status of the flags in bits 0 to 5. for example, if bit 0 is set (logic 1), then flag f0 is set. if bit 4 is set, then flag f4 is set. if bits 0 and 5 are set, then both flags f0 and f5 are set. the following table outlines the flag register read: flag bit (1 = set) number (0 = clear) 8-6 don? care 5f5 4f4 3f3 2f2 1f1 0f0 notes: 1. a soft reset (writing 00h to r05h) will not reset the flags in the flag register. a hard reset (reset pin low) is required to reset all the flags. the flags can also be reset by writing the proper word to the flag register as explained above. 2. while in trapezoid profile mode, flag f0 will be set, and flag f5 may be set. f5 is used for internal purposes. both flags will be cleared at the end of the profile. program counter register (r05h) the program counter, which is a write-only register, executes the preprogrammed functions of the controller. the program counter is used along with the control flags f0, f3, and f5 in the flag register (r00h) to change control modes. the user can write any of the following four commands to the program counter. value written to r05h action 00h software reset 01h enter init/idle mode 02h enter align mode (only from init/ idle mode) 03h enter control mode (only from init/ idle mode) these commands are discussed in more detail in the ?perating modes?section. register descriptions ?general control, output, filter, and commutator flag register (r00h) the flag register contains flags f0 through f5. this register is a read/write register. each flag is set and cleared by writing an 8-bit data word to r00h. when writing to r00h, the upper four bits are ignored by the hctl-1100, bits 0,1,2 specify the flag address, and bit 3 specifies whether to set (bit=1) or clear (bit=0) the addressed flag. flag descriptions f0 ?rapezoidal profile flag ?set by the user to execute trape- zoidal profile control. the flag is reset by the controller when the move is completed. the status of f0 can be monitored at the profile pin and in status register r07h bit 4. f1 ?nitialization/idle flag ?set/ cleared by the hctl-1100 to indicate execution of the initialization/idle mode. the status of f1 can be monitored at the initialization/idle pin and in bit 5 of the status register (r07h). the user should not attempt to set or clear f1. f2 ?nipolar flag ?set/cleared by the user to specify bipolar (clear) or unipolar (set) mode for the motor command port. f3 ?roportional velocity control flag ?set by the user to specify proportional velocity control. f4 ?old commutator flag ?set/ cleared by the user or auto- matically by the align mode. when set, this flag inhibits the internal commutator counters to allow open loop stepping of a
20 motor command register (r08h) the 8-bit motor command port consists of register r08h. the register is connected to external pins mc0-mc7. mc7 is the most significant bit. r08h can be read and written to; however, it should be written to only in the initialization/idle mode. during any of the four control modes, the hctl-1100 writes values to register r08h. the motor command port operates in two modes, bipolar and unipolar, when under control of internal software. bipolar mode allows the full range of values in r08h (-128d to +127d). the data written to the motor command port by the control algorithms is the internally computed 2?-complement motor command with an 80h offset added. this allows direct interfac- ing to a dac. connecting the motor command port to a dac, bipolar mode allows the full voltage swing (positive and negative). unipolar mode functions such that with the same dac circuit, the motor command output is restricted to positive values (80h to ffh) when in a control mode. unipolar mode is used with multi-phase motors when the commutator controls the direction of movement. (if needed, the sign pin could be used to indicate direction). in unipolar mode, the user can still write a negative value to r08h in init/idle mode. unipolar mode or bipolar mode is programmed by setting or clearing flag f2 in the flag register r00h. internally, the hctl-1100 operates on data of 24, 16 and 8- bit lengths to produce the 8-bit motor command, available externally. many times the computed motor command will be greater than 8 bits. at this point, the motor command is saturated by the controller. the saturated value output by the controller is not the full scale value 00h (00d), or ffh (255d). the saturated value is adjusted to 0fh (15d) (negative saturation) and f0h (240d) (positive saturation). saturation levels for the motor command port are in figure 4. table 3. status register status bit function 0p wm sign reversal inhibit 0 = off 1 = on 1 commutator phase configuration 0 = 3 phase 1 = 4 phase 2 commutator count configuration 0 = quadrature 1 = full 3 should always be set to 0 4 trapezoidal profile flag f0 1 = in profile control 5 initialization/idle flag f1 1 = in initialization/idle mode 6 stop flag 0 = set (stop triggered) 1 = cleared (no stop) 7 limit flag 0 = set (limit triggered) 1 = cleared (no limit) status register (r07h) the status register indicates the status of the hctl-1100. each bit decodes into one signal. all 8 bits are user readable and are decoded as shown below. only the lower 4 bits can be written to by the user to configure the hctl-1100. to set or clear any of the lower 4 bits, the user writes an 8-bit word to r07h. the upper 4 bits are ignored. each of the lower 4 bits directly sets/clears the corre- sponding bit of the status register as shown below. for example, writing xxxx0101 to r07h sets the pwm sign reversal inhibit, sets the commutator phase configuration to ? phase,?and sets the commutator count configuration to ?ull.
21 pwm motor command register (r09h) the pwm port outputs the motor command as a pulse width modulated signal with the correct sign of polarity. the pwm port consists of the pulse and sign pins and r09h. the pwm signal at the pulse pin has a frequency of external clock/100 and the duty cycle is (?0d) gives a 40% duty cycle signal at the pulse pin and forces the sign pin high. data outside the 64h (+100d) to 9ch (?00d) linear range gives 100% duty cycle. r09h can be read and written to. however, the user should only write to r09h when the controller is in the initiali- zation/idle mode. figure 5 shows the pwm output versus the internal motor command. figure 4. motor command port output. resolved into the 100 clocks. (for example, a 2 mhz clock gives a 20 khz pwm frequency.) the sign pin gives the polarity of the command. low output on sign pin is positive polarity. the 2?-complement contents of r09h determine the duty cycle and polarity of the pwm command. for example, d8h
22 when any control mode is being executed, the unadjusted internal 2?-complement motor command is written to r09h. because of the hardware limit on the linear range (64h to 9ch, 100d), the pwm port saturates sooner than the 8- bit motor command port (00h to ffh, +127d to ?28d). when the internal motor command saturates above 8 bits, the pwm port is saturated to the full 100% duty cycle level. figure 5 shows the actual values inside the pwm port. note that the unipolar flag, f2, does not affect the pwm port. for commutation of brushless motors with the pwm port, only use the pulse pin from the pwm port as the commutator already contains sign information. (see figure 9.) the pwm port has an option that can be used with h-bridge type amplifiers. the option is sign reversal inhibit, which inhibits the pulse output for one pwm period after a sign polarity reversal. this allows one pair of transistors to turn off before others are turned on and thereby avoids a short across the power supply. bit 0 in the status register (r07h) controls the sign reversal figure 6. sign reversal inhibit. figure 5. pwm port output.
23 in position control, integral velocity control, and trapezoidal profile control the digital filter is implemented in the time domain as shown below: mc n = (k/4)(x n ) [(a/256)(k/4)(x n? ) + (b/256)(mc n-1 )] [2] where: n = current sample time n-1 = previous sample time mc n = motor command output at n mc n-1 = motor command output at n-1 x n = (command position actual position) at n x n-1 = (command position actual position) at n-1 in proportional velocity control the digital compensation filter is implemented in the time domain as: mc n = (k/4)(y n ) [3] where: y n = (command velocity actual velocity) at n for more information on system sampling times, bandwidth, and stability, please consult avago application note 1032, design of the hctl-1000? digital filter parameters by the combination method . inhibit option. figure 6 shows the output of the pwm port when bit 0 is set. actual position registers read, clear: r12h,r13h,r14h preset : r15h,r16h,r17h the actual position register is accessed by two sets of registers in the hctl-1100. when reading the actual position from the hctl-1100, the host processor will read registers r12h(msb), r13h, and r14h(lsb). when presetting the actual position register, the processor will write to registers r15h(msb), r16h, and r17h(lsb). when reading the actual position registers, the order should be r14h, r13h, r12h. these registers are latched, such that, when reading register r14h, all three bytes will be latched so that count data does not change while reading three separate bytes. when presetting the actual position register, write to r15h and r16h first. when r17h is written to, all three bytes are simultaneously loaded into the actual position register. note that presetting the actual position registers is only allowed while the hctl-1100 is in init/ idle mode. the actual position registers can be simultaneously cleared at any time by writing any value to r13h. digital filter registers zero (a) r20h pole (b) r21h gain (k) r22h all control modes use some part of the programmable digital filter d(z) to compensate for closed loop system stability. the com- pensation d(z) has the form: ? a ? k ? z ? ? ? 256 ? d(z) = [1] ? b ? 4 ? z + ? ? 256 ? where: z = the digital domain operator k = digital filter gain (r22h) a = digital filter zero (r20h) b = digital filter pole (r21h) the compensation is a first-order lead filter which in combination with the sample timer t (r0fh) affects the dynamic step response and stability of the control system. the sample timer, t, determines the rate at which the control algorithm gets executed. all parameters, a, b, k, and t, are 8-bit scalars that can be changed by the user any time. as shown in equations [2] and [3], the digital filter uses previously sampled data to calculate d(z). this old internally sampled data is cleared when the initialization/idle mode is executed.
24 sample timer register (r0fh) the contents of this register set the sampling period of the hctl- 1100. the sampling period is: t = 16(t+1)(1/frequency of the external clock) [4] where: t = contents of register r0fh the sample timer has a limit on the minimum allowable sample time depending on the control mode being executed. the limits are given in table 4 below. the minimum value limits are to make sure the internal programs have enough time to complete proper execution. the maximum value of t (r0fh) is ffh (255d). with a 2 mhz clock, the sample time can vary from 64 sec to 2048 sec. with a 1 mhz clock, the sample time can vary from 128 sec to 4096 sec. digital closed-loop systems with slow sampling times have lower stability and a lower bandwidth than similar systems with faster sampling times. to keep the system stability and bandwidth as high as possible the hctl-1100 should typically be programmed with the fastest sampling time table 4. r0fh contents control mode minimum limit position control 07h(07d) proportional velocity control 07h(07d) trapezoidal profile control 0fh(15d) integral velocity control 0fh(15d) possible. this rule of thumb must be balanced by the needs of the velocity range to be controlled. velocities are specified to the hctl-1100 in terms of quadrature encoder counts per sample time. the faster the sampling time, the higher the slowest possible speed. hardware description the sample timer consists of a buffer and a decrement counter. each time the counter reaches 00h, the sampler timer value t (value written to r0fh) is loaded from the buffer into the counter, which immediately begins to decrement from t. writing to the sample timer register data written to r0fh will be latched into the internal buffer and used by the counter after it completes the present sample time cycle by decrementing to 00h. the next sample time will use the newly written data. reading the sample timer register reading r0fh gives the values directly from the decrementing counter. therefore, the data read from r0fh will have a value anywhere between t and 00h, depending where in the sample time cycle the counter is. example 1. on reset, the value of the timer is pre-set to 40h. 2. reading r0fh shows 3eh . . . 2bh . . . 08h . . . 3ch . . . synchronizing multiple axes synchronizing multiple axes with hctl-1100s can be achieved by using the sync pin as explained in the pin discussion section. some users may not only want to synchronize several hctl-1100s but also follow custom profiles for each axis. to do this, the user may need to write a new command position or command velocity during each sample time for the duration of the profile. in this case, data written to the hctl-1100 has to be coordinated with the sample timer. this is so that only one command position or velocity is received during any one sample period, and that it is written at the proper time within a sample period. at the beginning of each sample period, the hctl-1100 is performing calculations and executions. new command positions and velocities should not be written to the hctl-1100 during this time. if they are, the calculations may be thrown off and cause unpredictable control. the user can read the sample timer register to avoid writing too early during a sample period. since the sample timer register continuously counts down from its programmed value, the user can check if enough time has passed in the sample period to insure the completion of the internal calculations. the length of time needed by the hctl-1100
25 to do its calculations is given by the minimum limits of r0fh (sample timer register) as shown in table 4. for position control mode, the user should wait for the sample timer to count down 07h from its programmed value before writing the next command position or velocity. if the programmed sample timer value is 39h, wait until the sample timer register reads 32h. writing between 32h and 00h will make the command informa- tion available for the next sample period. commutator status register (r07h) commutator ring (r18h) x register (r1ah) y phase overlap (r1bh) offset (r1ch) max. phase advance (r1fh) velocity timer (r19h) the commutator is a digital state machine that is configured by the user to properly select the phase sequence for electronic commutation of multiphase motors. the commutator is designed to work with 2, 3, and 4- phase motors of various winding configurations and with various encoder counts. along with providing the correct phase enable sequence, the commutator provides programmable phase overlap, phase advance, and phase offset. phase overlap is used for better torque ripple control. it can also be used to generate unique state sequences which can be further decoded externally to drive more complex amplifiers and motors. phase advance allows the user to compensate for the frequency characteristics of the motor/ amplifier combination. by advancing the phase enable command (in position), the delay in reaction of the motor/amplifier combination can be offset and higher performance can be achieved. phase offset is used to adjust the alignment of the commutator output with the motor torque curves. by correctly aligning the hctl-1100? commutator output with the motor? torque curves, maximum motor output torque can be achieved. the inputs to the commutator are the three encoder signals, channel a, channel b, and index, and the configuration data stored in registers. figure 7. index pulse alignment to motor torque curves. the commutator uses both channels and the index pulse of an incremental encoder. the index pulse of the encoder must be physically aligned to a known torque curve location because it is used as the reference point of the rotor position with respect to the commutator phase enables. the index pulse should be permanently aligned during motor encoder assembly to the last motor phase. this is done by energizing the last phase of the motor during assembly and permanently attaching the encoder codewheel to the motor shaft such that the index pulse is active as shown in figures 7 and 8. fine tuning of alignment for commutation purposes is done electronically by the offset register (r1ch) once the com- plete control system is set up.
26 figure 9. pwm interface to brushless dc motors. each time an index pulse occurs, the internal commutator ring counter is reset to 0. the ring counter keeps track of the current position of the rotor based on the encoder feedback. when the ring counter is reset to 0, the commutator is reset to its origin (last phase going low, phase a going high) as shown in figure 10. figure 10. commutator configuration. figure 8. codewheel index pulse alignment. the output of the commutator is available as pha, phb, phc, and phd. the hctl-1100? commutator acts as the electrical equivalent of the mechanical brushes in a motor. therefore, the outputs of the commutator provide only proper phase sequencing for bidirectional operation. the magnitude information is provided to the motor via the motor command and pwm ports. the outputs of the commutator must be com- bined with the outputs of one of the motor ports to provide proper dc brushless and stepper motor control. figure 9 shows an example of circuitry which uses the outputs of the commutator with the pulse output of the pwm port to control a dc brushless or
27 0, 1, or 2 are written to the offset register, phase a will be enabled. when the values 3, 4 or 5 are written to the offset register, phase b will be enabled. and, when the values 6, 7, or 8 are written to the offset register, phase c will be enabled. no values larger than the value programmed into the ring register should be programmed into the offset register. phase advance registers (r19h, r1fh) the velocity timer register and maximum advance register linearly increment the phase advance according to the measured speed for rotation up to a set maximum. the velocity timer register (r19h) contains scalar data which determines the amount of phase advance at a given velocity. the phase advance is interpreted in the units set for the ring counter by bit #2 in r07h. the velocity is measured in revolu- tions per second. advance = n f v ? t [6] 16 (r19h + 1) where: ? t = [7] f external clk n f = full encoder counts/ revolution. v = velocity (revolutions/ second) the maximum advance register (r1fh) contains scalar data which sets the upper limit for phase advance regardless of rotor speed. figure 11 shows the relationship between the phase advance registers. note: if the phase advance feature is not used, set both r19h and r1fh to 0. stepper motor. a similar pro- cedure could be used to combine the commutator outputs pha- phd with a linear amplifier interface output (figure 16) to create a linear amplifier system. the commutator is programmed by the data in the following registers. figure 10 shows an example of the relationship between all the parameters. status register (r07h) bit #1- 0 = 3-phase configura- tion, pha, phb, and phc are active outputs. 1 = 4-phase configura- tion, pha ?phd are active outputs. bit #2- 0 = rotor position measured in quad- rature counts (4x decoding). 1 = rotor position measured in full counts (1 count = 1 codewheel bar and space.) bit #2 only affects the commuta- tor? counting method. this includes the ring register (r18h), the x and y registers (r1ah & r1bh), the offset register (r1ch), the velocity timer register (r19h), and the maximum advance register (r1fh). quadrature counts (4x decoding) are always used by the hctl- 1100 as a basis for position, velocity, and acceleration control. ring register (r18h) the ring register is defined as 1 electrical cycle of the commutator which corresponds to 1 torque cycle of the motor. the ring register is scalar and determines the length of the commutation cycle measured in full or quadra- ture counts as set by bit #2 in the status register (r07h). the value of the ring must be limited to the range of 0 to 7fh. x register (r1ah) this register contains scalar data which sets the interval during which only one phase is active. y register (r1bh) this register contains scalar data which set the interval during which two sequential phases are both active. y is phase overlap. x and y must be specified such that: x + y = ring/(# of phases) [5] these three parameters define the basic electrical commutation cycle. offset register (r1ch) the offset register contains two?-complement data which determines the relative start of the commutation cycle with respect to the index pulse. since the index pulse must be physically referenced to the rotor, offset performs fine alignment between the electrical and mechanical torque cycles. the hold commutator flag (f4) in the status register (r07h) is used to decouple the internal commutator counters from the encoder input. flag (f4) can be used in conjunction with the offset register to allow the user to advance the commutator phases open loop. this technique may be used to create a custom commuta- tor alignment procedure. for example, in figure 10, case 1, for a three-phase motor where the ring = 9, x = 3, and y = 0, the phases can be made to advance open loop by setting the hold commutator flag (f4) in the flag register (r07h). when the values
28 can be programmed as 0ah (10d) or aah (-86d), the latter satisfying equation 8. if bit #2 in the status register is set to allow the commutator to count in full counts, a higher resolution codewheel may be chosen for precise motor control without violating the commutator constraints equation (equation 8). example: suppose you want to commutate a 3-phase 15 deg/step variable reluctance motor attached to a 192 count encoder. 1. select 3-phase and quadrature mode for commutator by writing 0 to r07h. 2. with a 3-phase 15 degree/step variable reluctance motor the torque cycle repeats every 45 degrees or 8 times/revolution. 3. ring register (4)(192) counts/revolution = 8/revolution = 96 quadrature counts = 1 commutation cycle 4. by measuring the motor torque curve in both directions, it is determined that an offset of 3 mechanical degrees, and a phase overlap of 2 mechanical degrees is needed. (4) (192) offset = 3 360 ? 6 quadrature counts commutator constraints and use when choosing a three-channel encoder to use with a dc brush- less or stepper motor, the user should keep in mind that the number of quadrature encoder counts (4x the number of slots in the encoder? codewheel) must be an integer multiple (1x, 2x, 3x, 4x, 5x, etc.) of the number of pole pairs in the dc brushless motor or steps in a stepper motor. to take full advantage of the commutator? overlap feature, the number of quadrature counts should be at least 3 times the number of pole pairs in the dc brushless motor or steps in the stepper motor. for example, a 1.8 , (200 step/revolution) stepper motor should employ at least a 150 slot codewheel = 600 quadrature counts/revolution = 3 x 200 steps/revolution). there are several numerical constraints the user should be aware of to use the commutator. the parameters of ring, x, y, and max advance must be positive numbers (00h to 7fh). additionally, the following equation must be satisfied: (-128d) 80h 3/2 ring + offset max advance 7fh (127d) [8] in order to utilize the greatest flexibility of the commutator, it must be realized that the commutator works on a circular ring counter principle, whose range is defined by the ring register (r18h). this means that for a ring of 96 counts and a needed offset of 10 counts, numerically the offset register figure 11. phase advance vs. motor velocity.
29 to create the 3 mechanical degree offset, the offset register (r1ch) could be programmed with either a6h (-90d) or 06h (+06d). however, because 06h (+06d) would violate the commutator constraints equation 8, a6h (-90d) is used. (2 ) (4) (192) y = overlap = ? 4 360 x + y = 96/3 therefore, x = 28 y = 4 for the purposes of this example, the velocity timer and maximum advance are set to 0. operation flowchart the hctl-1100 executes any one of three setup routines or four control modes selected by the user. the three setup routines include: ?reset ?initialization/idle ?align. the four control modes available to the user include: ?position control ?proportional velocity control ?trapezoidal profile control ?integral velocity control the hctl-1100 switches from one mode to another as a result of one of the following three mechanisms: 1. the user writes to the program counter. 2. the user sets/clears flags f0, f3, or f5 by writing to the flag register (r00h). 3. the controller switches auto- matically when certain initial conditions are provided by the user. this section describes the func- tion of each setup routine and control mode and the initial conditions which must be pro- vided by the user to switch from figure 12. operation flowchart. one mode to another. figure 12 shows a flowchart of the setup routines and control modes, and shows the commands required to switch from one mode to another.
30 from reset mode, the hctl-1100 goes automatically to initialization/idle mode. initialization/idle executed by: - writing 01h to r05h, or - automatically executed after a hard reset, soft reset, or - limit pin goes low. the initialization/idle mode is entered either automatically from reset, by writing 01h to the program counter (r05h) under any conditions, or pulling the limit pin low. in the initialization/idle mode, the following occur: ?the initialization/idle flag (f1) is set. ?the pwm port r09h is set to 00h (zero command). ?the motor command port (r08h) is set to 80h (128d) (zero command). ?previously sampled data stored in the digital filter is cleared. it is at this point that the user should pre-program all the necessary registers needed to execute the desired control mode. the hctl-1100 stays in this mode (idling) until a new mode command is given. align executed by: - writing 02h to r05h the align mode is executed only when using the commutator feature of the hctl-1100. this mode automatically aligns mul- tiphase motors to the hctl- 1100? internal commutator. the align mode can be entered only from the initialization/idle mode by writing 02h to the program counter register (r05h). before attempting to enter the align mode, the user should clear all control mode flags and set both the command position registers (r0ch, r0dh, and r0eh) and the actual position registers (r12h, r13h, and r14h) to zero. after the align mode has been executed, the hctl-1100 will automatically enter the position control mode and go to position zero. by following this procedure, the largest movement in the align mode will be one torque cycle of the motor. the align mode assumes: the encoder index pulse has been physically aligned to the last motor phase during encoder/ motor assembly, the commutator parameters have been correctly preprogrammed (see the section called commutator for details), and a hard reset has been executed while the motor is stationary. the align mode first disables the commutator and with open loop control enables the first phase (pha) and then the last phase (phc or phd) to orient the motor on the last phase torque detent. each phase is energized for 2048 system sampling periods (t). for proper operation, the motor must come to a complete stop during the last phase enable. at this point the commutator is enabled and commutation is closed loop. the hctl-1100 then automati- cally switches from the align mode to position control mode. control modes control flags f0, f3, and f5 in the flag register (r00h) deter- mine which control mode is executed. only one control flag can be set at a time. after one of setup modes hard reset executed by: -pulling the reset pin low (required at power up) when a hard reset is executed (reset pin goes low), the following conditions occur: ?all output signal pins are held low except sign, data bus, and motor command. ?all flags (f0 to f5) are cleared. ?the pulse pin of the pwm port is set low while the reset pin is held low. after the reset pin is released (goes high) the pulse pin goes high for one cycle of the external clock driving the hctl-1100. the pulse pin then returns to a low output. ?the motor command port (r08h) is preset to 80h (128d). ?the commutator logic is cleared. ?the i/o control logic is cleared. ?a soft reset is automatically executed. soft reset executed by: - writing 00h to r05h, or - automatically called after a hard reset when a soft reset is executed, the following conditions occur: ?the digital filter parameters are preset to a (r20h) = e5h (229d) b (r21h) = k (r22h) = 40h (64d) ?the sample timer (r0fh) is preset to 40h (64d). ?the status register (r07h) is cleared. ?the actual position counters (r12h, r13h, r14h) are cleared to 0.
31 these control flags is set, the control modes are entered either automatically from align or from the initialization/idle mode by writing 03h to the program counter (r05h). position control mode flags: f0 cleared f3 cleared f5 cleared registers used: register function r00h r00d flag register r12h r18d read actual position msb r13h r19d read actual position r14h r20d read actual position lsb r0ch r12d command position msb r0dh r13d command position r0eh r14d command position lsb position control performs point- to-point position moves with no velocity profiling. the user specifies a 24-bit position example code to program position moves { begin } hard reset { hctl-1100 goes into init/idle mode } initialize filter, timer, command position registers write 03h to register r05h { hctl-1100 is now in position mode } write desired command position to command position registers { controller moves to new position } continue writing in new command positions { end } command, which the controller compares to the 24-bit actual position. the position error is calculated, the full digital lead compensation is applied and the motor command is output. the controller will remain position-locked at a destination until a new position command is given. the actual and command position data is 24-bit two?-complement data stored in six 8-bit registers. position is measured in encoder quadrature counts. the command position resides in r0ch (msb), r0dh, r0eh (lsb). writing to r0eh latches all 24 bits at once for the control algorithm. therefore, the com- mand position is written in the sequence r0ch, r0dh and r0eh. the command registers can be read in any desired order. the actual position resides in r12h (msb), r13h, and r14h (lsb). reading r14h latches the upper two bytes into an internal buffer. therefore, actual position proportional velocity mode flags: f0 cleared f3 set f5 cleared registers used: register function r00h r00d flag register r23h r35d command velocity lsb r24h r36d command velocity msb r34h r52d actual velocity lsb r35h r53d actual velocity msb proportional velocity control performs control of motor speed using only the gain factor, k, for compensation. the dynamic pole and zero lead compensation are not used. (see the ?igital filter section of this data sheet.) registers are read in the order of r14h, r13h, and r12h for cor- rect instantaneous position data. the largest position move possi- ble in position control mode is 7fffffh (8,388,607d) quadra- ture encoder counts.
32 the command and actual velocity are 16-bit two?-complement words. the command velocity resides in registers r24h (msb) and r23h (lsb). these registers are unlatched which means that the command velocity will change to a new velocity as soon as the value in either r23h or r24h is changed. the registers can be read or written to in any order. integral velocity mode flags: f0 cleared f3 cleared f5 set to begin move registers used: register function r00h r00d flag register r26h r38d acceleration lsb r27h r39d acceleration msb r3ch r60d command velocity integral velocity control performs continuous velocity profiling which is specified by a command velocity and command accelera- tion. figure 13 shows the capabil- ity of this control algorithm. the user can change velocity and acceleration any time to con- tinuously profile velocity in time. once the specified velocity is reached, the hctl-1100 will maintain that velocity until a new command is specified. changes between actual velocities occur at the presently specified linear acceleration. the command velocity is an 8-bit two?-complement word stored in r3ch. the units of velocity are quadrature counts/sample time. the units of velocity are quadra- ture counts/sample time. to convert from rpm to quadrature counts/sample time, use the formula shown below: vq = (vr)(n)(t)(0.01667/rpm-sec) [9] r24h r23h iiii iiii iiii ffff command velocity format where: vq = velocity in quadrature counts/sample time vr = velocity in rpm n = 4 times the number of slots in the codewheel (i.e., quadrature counts). example code for programming proportional velocity mode { begin } hard reset { hctl-1100 goes into init/idle mode } initialize filter, timer, command position registers write 03h to register r05h { hctl-1100 is now in position mode } write desired command velocity (if needed) set flag f3 {proportional velocity move begins} { system ramps to command velocity } continue writing new command velocities {end} t = the hctl-1100 sample time in seconds. (see the section on the hctl-1100? sample timer register). because the command velocity registers (r24h and r23h) are internally interpreted by the hctl-1100 as 12 bits of integer and 4 bits of fraction, the host processor must multiply the desired command velocity (in quadrature counts/sample time) by 16 before programming it into the hctl-1100? command velocity registers. the actual velocity is computed only in this algorithm and stored in scratch registers r35h (msb) and r34h (lsb). there is no fractional component in the actual velocity registers and they can be read in any order. the controller tracks the com- mand velocity continuously until new mode command is given. the system behavior after a new velocity command is governed only by the system dynamics until a steady state velocity is reached.
33 figure 13. integral velocity modes. the conversion from rpm to quadrature counts/sample time is shown in equation 9. the command velocity register (r3ch) contains only integer data and has no fractional component. while the overall range of the velocity command is 8 bits, two?- complement, the difference between any two sequential commands cannot be greater than 7 bits in magnitude (i.e., 127 decimal). for example, when the hctl-1100 is executing a command velocity of 40h (+64d), the next velocity com- mand must fall in the range of 7fh (+127d), the maximum command range, c1h (-63d), the largest allowed difference. the command acceleration is a 16-bit scalar word stored in r27h and r26h. the upper byte (r27h) is the integer part and the lower byte (r26h) is the fractional part provided for resolution. the integer part has a range of 00h to 7fh. the contents of r26h are internally divided by 256 to produce the fractional resolution. r27h r26h 0iiiiiii ffffffff/256 command acceleration format the units of acceleration are quadrature counts/sample time squared. to convert from rpm/sec to quadrature counts/[sample time] 2 , use the formula shown below: aq = (ar)(n)(t 2 )(0.01667/rpm- sec) [10] where: aq = acceleration in quadrature counts/[sample time] 2 ar = acceleration in rpm/sec n = 4 times the number of slots in the codewheel (i.e., quadrature counts) t = the hctl-1100 sample time in seconds. (see the section on the hctl-1100? sample timer register). because the command accelera- tion registers (r27h and r26h) are internally interpreted by the hctl-1100 as 8 bits of integer and 8 bits of fraction, the host processor must multiply the desired command acceleration (in quadrature counts/[sample time] 2 ) by 256 before programming it into the hctl-1100? command acceleration registers. internally, the controller performs velocity profiling through position control. each sample time, the internal profile generator uses the information which the user has programmed into the command velocity register (r3ch) and the command acceleration registers (r27h and r26h) to determine the value which will be automat- ically loaded into the command position registers (r0ch, r0dh, and r0eh). after the new command position has been generated, the difference between the value in the actual position registers (r12-r13h, and r14h) and the new value in the command position registers is calculated as the new position error. this new position error is used by the full digital compensa- tion filter to compute a new motor command output by this sample time. the register block in figure 3 further shows how the internal profile generator works in integral velocity mode. in control theory terms, integral compensa- tion has been added and there- fore, this system has zero steady- state error. although integral velocity control mode has the advantage over proportional velocity mode of zero steady state velocity error, its disadvantage is that the closed
34 loop stability is more difficult to achieve. in integral velocity control mode the system is actually a position control system and therefore the complete dynamic compensation d(z) is used. if the external stop flag f6 is set during this mode signalling an emergency situation, the controller automatically decelerates to zero velocity at the presently specified acceleration factor and stays in this condition until the flag is cleared. the user then can specify new velocity profiling data. trapezoid profile mode flags: f0 set to begin move f3 cleared f5 cleared registers used: register function r00h r00d flag register r07h r07d status register r12h r18d read actual position msb r13h r19d read actual position r14h r20d read actual position lsb r29h r41d final position lsb r2ah r42d final position r2bh r43d final position msb r26h r38d acceleration lsb r27h r39d acceleration msb r28h r40d maximum velocity trapezoid profile control performs point-to-point position moves and profiles the velocity trajectory to a trapezoid or triangle. the user specifies only the desired final position, acceleration and maximum velocity. the controller computes the necessary profile to conform to the command data. if maximum velocity is reached before the distance halfway point, the profile will be trapezoidal, otherwise the profile will be triangular. figure 14 shows the possible trajectories with trapezoidal profile control. the command data for trapezoidal profile control mode consists of a final position, a command acceleration, and a maximum velocity. the 24-bit, example code for programming integral velocity mode (begin) hard reset {hctl-1100 goes into init/idle mode} initialize filter, timer, command position registers write 03h to register r05h {hctl-1100 is now in position mode} write desired acceleration (if needed) write desired maximum velocity (if needed) set flag f5 {integral velocity move begins} {system ramps to maximum velocity} continue writing new accelerations and velocities { end }
35 figure 14. trapezoidal profile mode. two?-complement final position is written to registers r2bh, (msb), r2ah, and r29h (lsb). the 16- bit command acceleration resides in registers r27h (msb) and r26h (lsb). the command acceleration has the same integer and fraction format as discussed in the integral velocity control mode section. the 7-bit maximum velocity is a scalar value with the range of 00h to 7fh (0d to 127d). the maximum velocity has the units of quadrature counts per sample time, and resides in register r28h. the command data registers may be read or written to in any order. the internal profile generator produces a position profile using the present command position (r0ch-r0eh) as the starting point and the final position (r2bh-r29h) as the end point. once the desired data is entered, the user sets flag f0 in the flag register (r00h) to commence motion (if the hctl-1100 is already in position control mode). when the profile generator sends the last position command to the command position registers to complete the trapezoidal move, the controller clears flag f0. the hctl-1100 then automatically goes to position control mode with the final position of the trapezoidal move as the command position. when the hctl-1100 clears flag f0 it does not indicate that the motor and encoder are at the final position nor that the motor and encoder have stopped. the flag indicates that the command profile has finished. the motor and encoder? true position can only be determined by reading the actual position registers. the only way to determine if the motor and encoder have stopped is to read the actual position registers at successive intervals. the status of the profile flag can be monitored both in the status register (r07) and at the external profile pin at any time. while the profile flag is high no new command data should be sent to the controller. each sample time, the internal profile generator uses the information which the user has programmed into the maximum velocity register (r28h), the command acceleration registers (r27h and r26h), and the final position registers (r2bh, r2ah, and r29h) to determine the value which will be automatically loaded into the command position registers (r0eh, r0dh, and r0ch). after the new command position has been generated, the difference between the value in the actual position registers (r12h, r13h, and r14h) and the new value in the command position registers is calculated as the new position error. this new position error is used by the full digital compensation filter to compute a new motor command output for the sample time. (the register block diagram in figure 3 further shows how the internal profile generator works in trapezoidal profile mode.)
36 example code for programming trapezoid moves { begin } hard reset { hctl-1100 goes into init/idle mode } inititalize filter, timer, command position registers write 03h to register r05h { hctl-1100 is now in position mode } { profile #1} write desired acceleration write desired maximum velocity write final position set flag f0 {trapezoid move begins, prof pin goes high} poll prof pin until it goes low (move is complete) { profile #2} write desired acceleration write desired maximum velocity write final position set flag f0 {trapezoid move begins, prof pin goes high} poll prof pin until it goes low (move is complete) { repeat } . . . . { end } applications of the hctl-1100 interfacing the hctl-1100 to host processors the hctl-1100 looks to the host microprocessor like a bank of 8- bit registers to which the host processor can read and write (i.e., the host processor treats the hctl-1100 like ram). the data in these registers controls the operation of the hctl-1100. the host processor communicates to the hctl-1100 over a bidirectional multiplexed 8-bit data bus. the four i/o control lines. ale, cs, oe, and r/w execute the data transfers (see figure 15).
37 there are three different timing configurations which can be used to give the user greater flexibility to interface the hctl-1100 to most microprocessors (see timing diagrams). they are differentiated from one another by the arrangement of the ale signal with respect to the cs signal. the three timing configurations are listed below. 1. ale, cs non-overlapped 2. ale, cs overlapped 3. ale within cs any i/o operation starts by asserting the ale signal which starts sampling the external bus into an internal address latch. rising ale or falling cs during ale stops the sampling into the address latch. cs low after rising ale samples the external bus into the data latch. rising cs stops the sampling into the data latch, and starts the internal synchronous process. in the case of a write, the data in the data latch is written into the addressed location. in the case of a read, the addressed location is written into an internal output latch. oe low enables the internal output latch onto the external bus. the oe signal and the internal output latch allow the i/o port to be flexible and avoid bus conflicts during read operations. it is important that the host microprocessor does not attempt to perform too many i/o operations in a single sample time of the hctl-1100. each i/o operation interrupts the execution of the hctl-1100? internal code for 1 clock cycle. although extra clock cycles have been allotted in each sample time for i/o operations, the number of extra cycles is reduced as the value programmed into the sample timer register (r0fh) is reduced. table 5 shows the maximum number of i/o operations allowed under the given conditions. the number of external clock cycles available for i/o operations in any of the four control modes can be increased by increasing the value in the sample timer register (r0fh). for every unit increase in the sample timer register (r0fh) above the minimums shown in table 5 the user may perform 16 additional i/o operations per sample time. data written to the 8-bit motor command port by the control algorithms is the internally computed 2?-complement motor command with an 80h offset added. this allows direct interfacing to a dac. figure 16 shows a typical dac interface to the hctl-1100. an inexpensive dac, such as mc1408 or equivalent, has its digital inputs directly connected to the motor command port. the dac pro- duces an output current which is converted to a voltage by an operational amplifier. r o and r g control the analog offset and gain. the circuit is easily adjusted for +5 v to ? v operation by first writing 80h to r08h and adjusting r o for 0 v output. then ffh is written to r08h and r g is adjusted until the output is 5 v. note that 00h in r08h corresponds to ? v out. figure 17 shows an example of how to interface the hctl-1100 to an h-bridge amplifier. an h- bridge amplifier allows bipolar motor operation with a unipolar power supply. interfacing the hctl-1100 to amplifiers and motors the motor command port is the ideal interface to an 8-bit dac, configured for bipolar output. the table 5. maximum number of i/o allowed maximum number sample timer of i/o operations register value operating mode allowed per sample 07h (07d) position control or 5 prop. vel. control position control or 133 prop. vel. control ofh (15d) trapezoidal prof. or integral 6 vel. control
38 123456789101112 rc v cc ph oe a k logic k a udn2954w sign pulse dc motor +v motor +5 v 10 f 30 k figure 15. i/o port block diagram. figure 16. linear amplifier interface. figure 17. h-bridge amplifier interface. v cc v ref+ i o v ee comp v ref+ gnd a 8 (lsb) a 7 a 6 a 5 a 4 a 3 a 2 a 1 (msb) 15 2 2.5 k 13 14 2.5 k +5 v 4 3 ?12 v 75 pf 16 18 12 19 11 20 10 21 9 22 8 23 7 24 6 25 5 mc1408 (lsb) mc 0 mc 1 mc 2 mc 3 mc 4 mc 5 mc 6 (msb) mc 7 hctl-1000 +5 v 5 k r o 5 k r l v out 6 2 3 x? x+ lf356
39 additional information from avago technologies application notes and application briefs regarding the hctl-1100 are from the avago technologies motion control factory. please contact your local avago sales representative for more information. - m003 - z80 interface to the hctl-1100 - m005 - sample timer and digital filter - m009 - list of board level v endors using hctl-1100 - m010 - hctl-1100 trouble shooting guide - m012 - commutator port in the hctl-1100 - m015 - interfacing the hctl- 1100 to the 8051 - m016 - 8051/hctl-1100 stand alone controller with rs232 port - m018 - the effects of high- frequency noise on the hctl- 1100 - m021 - interfacing the hctl- 1100 to 68hc11. - m024 - using the hctl-1100 with dc brush motors. - m025 - using the hctl-1100 with dc brushless motors. - m026 - using the hctl-1100 with stepper motors. ordering information hctl-1100: 40 pin dip package hctl-1100#plc: 44 pin plcc package
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries . data subject to change. copyright ? 2006 avago technologies limited. all rights reserved. obsoletes 5988-4215en 5988-5896en june 7, 2006

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